The present invention relates to a parallel arithmetic device, a data processing system with the parallel arithmetic device, and a computer-readable medium storing a data processing program.
A coarse-grained dynamically reconfigurable processor (parallel arithmetic device or array-type processor) forms a circuit by dynamically changing the processing of each of a plurality of processor elements and the relation of coupling therebetween in accordance with an externally input object code. Hence, the dynamically reconfigurable processor can reuse circuit resources to perform a complicated arithmetic process with a small-scale circuit. An exemplary configuration of the dynamically reconfigurable processor is disclosed, for instance, in Japanese Patents Nos. 3921367 and 3861898.
A single-instruction multiple-data (SIMD) processor, which performs a plurality of arithmetic processes in parallel upon receipt of a single-operation instruction, is disclosed in Japanese Patents Nos. 4292197 and 4699002 and in Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2010-539582.